Hybrid multiple bit-depth video processing architecture

ABSTRACT

An apparatus including a processor and a memory. The processor may be configured to process pixel data comprising eight or more bits. For pixel data having bit-depths greater than eight bits, a number of most significant bits (MSBs) of a pixel are presented as a first byte and a number of least significant bits (LSBs) of the pixel are packed with LSBs from one or more other pixels into a second byte. The memory may be coupled to the processor and configured to store the first byte in response to a first pointer and the second byte in response to a second pointer. The first byte and the second byte are stored independently in the memory.

FIELD OF THE INVENTION

The present invention relates to a video processing architecturegenerally and, more particularly, to a hybrid multi-depth(8-bit/multi-bit) video processing architecture.

BACKGROUND OF THE INVENTION

Conventional video processing is restricted to 8-bit when videocompression and de-compression (as defined by existing standards such asMPEG-2, MPEG-4, and H.264) are involved. Conventional digital video,whether in YUV or RGB format, represented in an 8-bit format works wellwith digital circuitry and memory that access data in chunks of 8 bits(i.e., bytes). However, new generation display technology, such as LCDor Plasma, use more bit-depth to provide a higher contrast range anddeeper dynamic range.

Conventional techniques for video processing include (i) restricting allvideo to 8-bit and sacrificing video quality, (ii) storing each pixelwith multiple bytes and (iii) making every memory access 10-bit orwider. Making every access 10-bit or wider wastes memory bandwidth whenonly 8-bit data is used for MPEG. Storing multiple bytes per pixelwastes memory space. Other disadvantages of the conventional techniquescan include complex logic for extracting 8-bit data from multi-bit data,and quantization noise and artifacts on the display unit.

It would be desirable to have a system that can efficiently handle amixture of video precision.

SUMMARY OF THE INVENTION

The present invention concerns an apparatus including a processor and amemory. The processor may be configured to process pixel data comprisingeight or more bits. For pixel data having bit-depths greater than eightbits, a number of most significant bits (MSBs) of a pixel are presentedas a first byte and a number of least significant bits (LSBs) of thepixel are packed with LSBs from one or more other pixels into a secondbyte. The memory may be coupled to the processor and configured to storethe first byte in response to a first pointer and the second byte inresponse to a second pointer. The first byte and the second byte arestored independently in the memory.

The objects, features and advantages of the present invention includeproviding a hybrid multi-depth (8-bit/multi-bit) video processingarchitecture that may (i) handle 8-bit/multi-bit data efficiently, (ii)make optimal use of memory bandwidth, (iii) eliminate quantization noiseor artifact when displaying 8-bit video on a multi-bit display panel,(iv) be used in non television or DVD applications such as hand-heldvideo players and/or (v) provide for future expansion.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features and advantages of the presentinvention will be apparent from the following detailed description andthe appended claims and drawings in which:

FIG. 1 is a block diagram illustrating a multi-precision data path inaccordance with preferred embodiments of the present invention;

FIG. 2 is a detailed block diagram illustrating a processor inaccordance with a preferred embodiment of the present invention;

FIG. 3 is a more detailed block diagram illustrating a processor inaccordance with another preferred embodiment of the present invention;and

FIGS. 4(A-B) are block diagrams illustrating memory buffer structures inaccordance with preferred embodiments of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The present invention may address several problems with conventionaltechniques including memory bandwidth optimization, memory accesslatency minimization, random access support, and future growth support.In general, an important resource in a digital video system is memorybandwidth. Since memory bandwidth is important, enabling 8-bit dataaccess within a higher resolution data structure is desirable. Forexample, if a video display uses 12-bit data, the most significant 8bits may be accessed by a video compression engine while the whole 12bits are accessed by the display processing unit. The video compressionengine accesses only the data to be compressed rather than accessing thewhole 12 bits and throwing away the extra 4 bits of data. Otherwise, 25%of the memory bandwidth is wasted.

The present invention may minimize memory access latency by allowingaccess to data without pre-processing the data structure. For example,in the 12-bit video system example, hardware in accordance with thepresent invention may be configured to read 8-bit data rather thanreading 12-bit data, re-assembling and re-packing the 12-bit data in8-bit fashion and sending the 8-bit data to an 8-bit processing unit.

The present invention may provide random access support. In a videoprocessing application (e.g., a pan and scan display of a 16:9 videoimage on a 4:3 LCD display panel) sub-window video data may be read orwritten. Multi precision video data may make calculating pixelboundaries difficult for the hardware. The display window may be movedfrom frame to frame (e.g., as in a DVD play back system). The presentinvention generally manages the video data structure with twoindependent pointers. A first pointer may be implemented for accessing afirst buffer storing the 8-bit MSBS of each pixel. A second pointer maybe implemented for accessing a second buffer storing packed LSB data fortwo or more pixels. The 8-bit MSB of each pixel is on a byte boundary,and the 4-bit LSB (for 12-bit/pixel) data of two pixels is on a byteboundary also. The present invention eases the calculation of byteaddresses of source and destination for a transfer.

The present invention may provide support for a future growth path. Theindustry is moving from 8-bit, to 10-bit, to 12-bit processing. Thepresent invention generally provides a new data structure that may beeasily adapted without major re-design work.

Referring to FIG. 1, a block diagram is shown illustrating a circuit 100in accordance with a preferred embodiment of the present invention. Inone example, the circuit 100 may be implemented as a multi-precisiondata path. In one example, the circuit 100 may be implemented as part ofa video processing system. In general, the circuit 100 may be configuredto handle a mixture of video precision (e.g., bit-depths). For example,the circuit 100 may be configured to handle a variety of videobit-depths (e.g., 8-bit, 10-bit, 12-bit, etc.).

The circuit 100 may have an input 102 that may receive a signal (e.g.,VIDEO_IN) and an output 104 that may present a signal (e.g., VIDEO_OUT).The signal VIDEO_IN may comprise, in one example, a multi-bit (e.g.,8-bit or other bit-depth) data stream. In one example, the signalVIDEO_IN may comprise a video input data stream. The signal VIDEO_OUTmay comprise an 8-bit or other bit-depth data stream. In one example,the signal VIDEO_OUT may comprise a video output data stream. The signalVIDEO_OUT may be configured to drive new generation display technology,such as LCD or Plasma displays. The circuit 100 may be configured togenerate the signal VIDEO_OUT in response to the signal VIDEO_IN.

In one example, the circuit 100 may comprise a circuit 106 and a circuit108. The circuit 106 may be implemented as a processor circuit. In oneexample, the circuit 106 may comprise a media processor. The circuit 108may be implemented as a storage device. In one example, the circuit 108may comprise one or more memory devices (e.g., dynamic random accessmemory (DRAM), double data rate (DDR) DRAM, etc.). However, other typesof storage devices (e.g., hard drive, DVD, etc.) may be implemented tothe design criteria of a particular implementation.

The circuit 106 may have a first input that may receive the signalVIDEO_IN, a first output that may present a signal (e.g., DMA_HI_OUT), asecond output that may present a signal (e.g., DMA_LO_OUT), a secondinput that may receive a signal (e.g., DMA_HI_IN), a third input thatmay receive a signal (e.g., DMA_LO_IN), a fourth input that may receivea signal (e.g., COMP_IN), a third output that may present a signal(e.g., COMP_OUT) and a fifth input that may receive a signal (e.g.,BITSTREAM). As would be apparent to those skilled in the relevantart(s), the signals illustrated in FIG. 1 represent logical data flows.The logical data flows are generally representative of physical datatransferred between the circuit 106 and the circuit 108 by, for example,address, data, and control signals and/or busses. The system representedby the circuit 100 may be implemented in hardware, software or acombination of hardware and software according to the teachings of thepresent disclosure, as would be apparent to those skilled in therelevant art(s).

In one example, the circuit 108 may be configured to couple (orinterface) to the circuit 106. In another example, the circuit 106 maybe configured to interface with the circuit 108. The circuit 108 mayhave a first input that may receive the signal DMA_HI_OUT, a secondinput that may receive the signal DMA_LO_OUT, a first output that maypresent the signal DMA_HI_IN, a second output that may present thesignal DMA_LO_IN, a third output that may present the signal COMP_IN, athird input that may receive the signal COMP_OUT and a fourth outputthat may present the signal BITSTREAM. In one example, the signalBITSTREAM may comprise data received in the signal COMP_OUT.

The signal DMA_HI_OUT may comprise a number of most significant bits(MSB) of the signal VIDEO_IN. For example, the signal DMA_HI_OUTgenerally comprises the eight most significant bits of each data sample(e.g., pixel) of the signal VIDEO_IN. The signal DMA_LO_OUT may comprisea number of least significant bits (LSB) for a number of data samples ofthe signal VIDEO_IN. For example, each byte of the signal DMA_LO_OUT maycomprise two least significant bits for each of four data samples (for a10-bit signal VIDEO_IN) or four least significant bits for each of twodata samples (for a 12-bit signal VIDEO_IN). The signals DMA_HI_OUT andDMA_LO_OUT may further comprise independent pointers for controllingstorage of the respective data by the circuit 108. The signal DMA_HI_INgenerally comprises the eight most significant bits of a multi-bit(e.g., 8-bit, 10-bit, 12-bit, etc.) data sample. The signal DMA_LO_INmay comprise least significant bits (LSB) of a number of data samplespacked 8-bits wide.

The signal COMP_IN generally comprises the eight most significant bitsof one or more multi-bit data samples. The signal COMP_OUT generallycomprises a compressed bit stream generated in response to the signalCOMP_IN. In one example, the signal COMP_OUT may be compliant with oneor more predetermined compression standards (e.g., MPEG-2, MPEG-4,H.263, H.264, etc.). The signal BITSTREAM may comprise a compressed databit stream compliant with one or more predetermined compressionstandards (e.g., MPEG-2, MPEG-4, H.263, H.264, etc.).

Referring to FIG. 2, a detailed block diagram is shown illustrating anexample of an embodiment of the circuit 106 of FIG. 1 in accordance witha preferred embodiment of the present invention. In one example, thecircuit 106 may comprise a circuit (or block) 110 and a circuit (orblock) 112. The circuit 110 may be implemented, in one example, as adirect memory access (DMA) circuit (or engine). The circuit 112 may beimplemented, in one example, as a compression/decompression (CODEC) anddisplay processing circuit.

The circuit 110 may have a first input that may receive the signalVIDEO_IN, a second input that may receive the signal DMA_HI_IN, a thirdinput that may receive the signal DMA_LO_IN, a first output that maypresent the signal DMA_HI_OUT, a second output that may present thesignal DMA_LO_OUT and a third output that may present a signal (e.g.,R_VIDEO). The signal R_VIDEO may comprise multi-bit video (or other)data. The circuit 110 may be configured to generate the signalsDMA_HI_OUT and DMA_LO_OUT in response to the signal VIDEO_IN. Thecircuit 110 may be configured to generate the signal R_VIDEO in responseto the signals DMA_HI_IN and DMA_LO_IN. In one example, the signalR_VIDEO may comprise multi-bit data reconstructed (or recovered, orreassembled) from the signals DMA_HI_IN and DMA_LO_IN. For example, thesignal R_VIDEO may comprise a time-delayed version of the signalVIDEO_IN.

The circuit 112 may have a first input that may receive the signalVIDEO_IN, a second input that may receive the signal R_VIDEO, a thirdinput that may receive the signal COMP_IN, a fourth input that mayreceive the signal BITSTREAM, a first output that may present the signalCOMP_OUT and a second output that may present the signal VIDEO_OUT. Thecircuit 112 may be configured to generate the signal VIDEO_OUT inresponse to one or more of the signals VIDEO_IN, R_VIDEO and BITSTREAM.The circuit 112 may be configured to generate the signal COMP_OUT inresponse to the signal COMP_IN.

Referring to FIG. 3, a more detailed block diagram is shown illustratingan example of another embodiment of the circuit 106 in accordance withanother preferred embodiment of the present invention. In one example,the circuit 110 may comprise a circuit (or block) 120, a circuit (orblock) 122 and a circuit (or block) 124. In one example, the circuit 112may comprise a circuit (or block) 130, a circuit (or block) 132, acircuit (or block) 134 and a circuit (or block) 136. The circuit 120 maybe implemented, in one example, as a DMA engine. The circuit 122 may beimplemented, in one example, as a DMA engine. The circuit 124 may beimplemented, in one example, as a DMA engine. The circuit 130 may beimplemented, in one example, as a display processing circuit. Thecircuit 132 may be implemented, in one example, as a video compressioncircuit. In one example, the circuit 132 may be implemented as astandard compliant (e.g., MPEG, H.264, etc.) compression circuit (ordevice). The circuit 134 may be implemented, in one example, as a videodecompression circuit. In one example, the circuit 134 may beimplemented as a standard compliant (e.g., MPEG, H.264, etc.)decompression circuit (or device). The circuit 136 may be implemented,in one example, as a dithering circuit. The blocks 120-136 may beimplemented using conventional techniques and the teachings of thepresent disclosure.

The signal VIDEO_IN may be presented to an input of the circuit 120, aninput of the circuit 122 and a first input of the circuit 130. Thecircuit 120 may have an output that may present the signal DMA_HI_OUT.In one example, the circuit 120 may comprise an 8-bit DMA engineconfigured to manipulate the eight most significant bits (MSBs) of eachpixel in the signal VIDEO_IN. The circuit 122 may have an output thatmay present the signal DMA_LO_OUT. In one example, the circuit 122 maybe configured to manipulate (e.g., pack) the remaining least significantbits (LSBs) of each pixel in the signal VIDEO_IN. For example, thecircuit 122 may be configured to pack LSBs from two or more pixels intoa single byte. The circuits 120 and 122 may be configured to generateindependent pointers to independent buffers implemented in the circuit108. The circuit 124 may have a first input that may receive the signalDMA_HI_IN, a second input that may receive the signal DMA_LO_IN and anoutput that may present the signal R_VIDEO to a second input of thecircuit 130. The circuit 124 may be configured to generate pointers foraccessing the buffers implemented in the circuit 108.

The video (or other) input data of the signal VIDEO_IN may be separatedby the circuit 110 into a first portion comprising the 8 MSBs and asecond portion comprising the remaining LSBs. For example, the 8 MSBsmay be separated and then packed together as data bytes and sent to thememory 108 by the DMA engine 120. The LSB may also be extracted andpacked together as a data byte and sent to the memory 108 by the DMAengine 122. For example, in a 10-bit video system, the extra 2 LSBs of 4pixels may be packed to form a single byte and sent to the memory 108.

The circuit 132 may have an input that may receive the signal COMP_INand an output that may present the signal COMP_OUT. The circuit 132 maybe configured to generate the signal COMP_OUT from the signal COMP_INusing one or more compression standards (e.g., MPEG-2, MPEG-4, H.264,etc.). The circuit 134 may have an input that may receive the signalBITSTREAM and an output that may present a signal (e.g., D_VIDEO) to aninput of the circuit 136. The circuit 134 may be configured todecompress (or decode) the signal BITSTREAM in accordance with one ormore decompression standards (e.g., MPEG-2, MPEG-4, H.264, etc.). Thesignal D_VIDEO may comprise an uncompressed 8-bit video signal.

The circuit 136 may have an output that may present a multi-bit datasignal (e.g., MULTI-BITS) to a third input of the circuit 130. In oneexample, the signal MULTI_BITS may comprise a multi-bit video signal. Inone example, the signal MULTI_BITS has a greater bit-depth than thesignal D_VIDEO. In one example, the circuit 136 may be configured to addrandom noise to the least significant bits of the pixels in the signalMULTI_BITS to improve the appearance of the pixels when displayed. Forexample, decoding an MPEG compressed signal provides 8-bit data. Ifzeroes are added as the least significant bits, discrete steps may bevisible on the display. A contour may be seen if the data is for a 2Dimage. By adding random noise to the least significant bits, the stepsand/or contour effect may be hidden (obscured). In another example, thecircuit 136 may be configured to add zeroes as the least significantbits and perform horizontal and vertical filtering. In one example, asort of bank notch filtering may be implemented to filter out noise(e.g., the contour effect) in a predetermined frequency range.

The circuit 130 may have an output that may present the signalVIDEO_OUT. The circuit 130 may be configured to select between thesignals VIDEO_IN, R_VIDEO and MULTI_BITS as a source for generating thesignal VIDEO_OUT. In one example, the circuit 130 may be userprogrammable. In one example, the circuit 130 may comprise one or morecircuits (or blocks) such as a de-interlacer (e.g., for a source of 480i or 1080 i), a noise reduction filter, a vertical and horizontal scaler(e.g., for adjusting the input image to the output display panel), amixer (e.g., for combining the video plane, OSD, etc.), a raster timingcontroller, a format converter (e.g., 422 to 444, etc.), a gammacorrection circuit, and/or a panel output controller.

The circuit 132 and the circuit 134 may be configured to access only thedata buffer in the memory 108 containing the 8 MSBs. Since the MSBs datais stored separately from the LSBs data, future expansion of databit-depth (e.g., to 12-bit, 14-bit, etc.) may be transparent to thecircuits 132 and 134. The circuit 136 may be configured to use adithering method, when displaying decompressed 8-bit video, to expandthe 8-bit video to the full data depth of an attached display. Ditheringmay be done by inserting extra random LSBs to the 8-bit data. Theadvantage of dithering is to hide the quantization noise. For example, aramp up video signal may be seen as discrete steps on high contrastplasma panels. The circuit 136 may be configured to effectively concealsuch a “staircase” artifact.

In one example, the circuit 106 may be configured to support directvideo display from the memory buffer 108. In one example, the memory 108may be used as a buffer (e.g., time delay) for the input signalVIDEO_IN. In such a case, the DMA engine 124 may be configured toseparately access both MSBs and LSBs data and recombine the data to fulldepth before displaying.

Referring to FIGS. 4(A-B), block diagrams are shown illustrating examplememory data structures in accordance with a preferred embodiment of thepresent invention. In one example, the system 100 may be configured fora 10-bit video input signal. When the system 100 is configured for10-bit video input signal, a memory data structure may be implementedsuch that the data is stored in 8-bit (byte) quantities (e.g., FIG. 4A).For example, when the data structure implemented is 10-bits wide, the 8most significant bits of a video pixel may be stored as one byte in afirst buffer 140 and the 2 least significant bits of four pixels may becombined and stored as a single byte in a second buffer 142.

In another example, the system 100 may be configured for a 12-bit videoinput signal. When the system 100 is configured for 12-bit video inputsignal, a memory data structure may be implemented such that the data isstored in 8-bit (byte) quantities (e.g., FIG. 4B). For example, when thedata structure implemented is 12-bits wide, the 8 most significant bitsof a video pixel may be stored as one byte in the buffer 140 and the 4least significant bits of two pixels may be combined and stored as asingle byte in the buffer 142.

The data structure stored in the memory 108 generally has separatebuffers for the 8 MSBs and the remaining LSBs. In one example, the twobuffers may be stored as 2-dimensional strip buffers to enable efficientMPEG motion compensation access. In one example, access may be achievedwith a small 16×16 or 8×8 2-dimensional strip.

The present invention generally provides a system that may effectivelydeal with video data depth beyond 8-bit while maintaining efficienthandling of 8-bit data. The present invention may provide advantagesthat may include providing an architecture that is ready for futureexpansion, providing effective memory bandwidth usage, providingdecompressed data expansion and providing simple data format conversion.For example, increasing the video from 10-bit to 12-bit generallyinvolves changing only the DMA engine. The major modules such as MPEGcompression/decompression engines are untouched. Each module may beconfigured to fetch the minimum data for performing the respectiveoperation. 8-bit MPEG video may be expanded efficiently to hide thequantization noise and other artifact. 8-bit and multi-bit data may beexchanged and packing/unpacking performed with simple DMA engine logicbecause upper and lower bit data are stored independently in memory.

The functions performed by the data flow diagrams of FIGS. 1-3 may beimplemented using a conventional general purpose digital computerprogrammed according to the teachings of the present specification, aswill be apparent to those skilled in the relevant art(s). Appropriatesoftware coding can readily be prepared by skilled programmers based onthe teachings of the present disclosure, as will also be apparent tothose skilled in the relevant art(s).

The present invention may also be implemented by the preparation ofapplication specific integrated circuits (ASICs), field programmablegate arrays (FPGAs), or by interconnecting an appropriate network ofconventional component circuits, as is described herein, modificationsof which will be readily apparent to those skilled in the art(s).

The present invention thus may also include a computer product which maybe a storage medium including instructions which can be used to programa computer to perform a process in accordance with the presentinvention. The storage medium can include, but is not limited to, anytype of disk including floppy disk, optical disk, CD-ROM,magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, Flash memory,magnetic or optical cards, or any type of media suitable for storingelectronic instructions.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

1. An apparatus comprising: a processor configured to process pixel datacomprising eight or more bits, wherein for pixel data having bit-depthsgreater than eight bits, a number of most significant bits (MSBs) of apixel are presented as a first byte and a number of least significantbits (LSBs) of said pixel are packed with LSBs from one or more otherpixels into a second byte; and a memory coupled to said processor andconfigured to store said first byte in response to a first pointer andsaid second byte in response to a second pointer, wherein said firstbyte and said second byte are stored independently in said memory. 2.The apparatus according to claim 1, wherein said apparatus is part of avideo processing data path.
 3. The apparatus according to claim 1,wherein said second byte comprises two LSBs from four pixels for 10-bitpixel data and four LSBs from two pixels for 12-bit pixel data.
 4. Theapparatus according to claim 1, wherein said memory comprises a firstbuffer configured to store a plurality of first bytes and a secondbuffer configured to store a plurality of second bytes.
 5. The apparatusaccording to claim 1, wherein said processor comprises a direct memoryaccess engine configured to partition said pixel data into said firstbyte and said second byte.
 6. The apparatus according to claim 5,wherein said direct memory access engine is further configured toreassemble said pixel data from said first byte and said second byte. 7.The apparatus according to claim 1, wherein: said processor comprises acompression circuit configured to generate a compressed bitstream from aplurality of first bytes read from said memory; and said memory isfurther configured to store said compressed bitstream.
 8. The apparatusaccording to claim 1, wherein: said processor comprises a decompressioncircuit configured to generate an 8-bit data stream in response to acompressed bitstream read from said memory; and said memory is furtherconfigured to store said compressed bitstream.
 9. The apparatusaccording to claim 8, wherein said processor further comprises: adithering circuit configured to generate a multi-bit data stream inresponse to said 8-bit data stream; and a display processing circuitconfigured to generated a video signal in response to said multi-bitdata stream.
 10. The apparatus according to claim 1, wherein saidprocessor comprises: a first DMA engine configured to process pixel datacomprising eight or more bits, wherein for pixel data having bit-depthsgreater than eight bits, a number of most significant bits (MSBs) of apixel are presented as a first byte and a number of least significantbits (LSBs) of said pixel are packed with LSBs from one or more otherpixels into a second byte; a second DMA engine configured to reconstructpixel data having a bit-depth greater than eight bits from said firstbyte and said second byte; a compression/decompression (CODEC) circuitconfigured (i) to generate a compressed bitstream from a plurality offirst bytes and (ii) to generate an 8-bit data stream from saidcompressed bitstream; a dithering circuit configured to generate amulti-bit data stream from said 8-bit data stream; and a displayprocessor configured to generate a video output signal, wherein saidvideo output signal is generated in response to (i) said pixel data in afirst mode, (ii) reconstructed pixel data in a second mode and (iii)said multi-bit data stream in a third mode.
 11. A video processing datapath comprising: means for processing pixel data comprising eight ormore bits, wherein for pixel data having bit-depths greater than eightbits, a number of most significant bits (MSBs) of a pixel are presentedas a first byte and a number of least significant bits (LSBs) of saidpixel are packed with LSBs from one or more other pixels into a secondbyte; and means for storing said first byte according to a first pointerand said second byte according to a second pointer, wherein said firstbyte and said second byte are stored independently in a memory.
 12. Amethod for processing multi-depth video data comprising the steps of:processing pixel data comprising eight or more bits, wherein for pixeldata having bit-depths greater than eight bits, a number of mostsignificant bits (MSBs) of a pixel are presented as a first byte and anumber of least significant bits (LSBs) of said pixel are packed withLSBs from one or more other pixels into a second byte; and storing saidfirst byte according to a first pointer and said second byte accordingto a second pointer, wherein said first byte and said second byte arestored independently in a memory.
 13. The method according to claim 12,wherein said second byte comprises two LSBs from four pixels for 10-bitpixel data and four LSBs from two pixels for 12-bit pixel data.
 14. Themethod according to claim 12, wherein said memory comprises a firstbuffer configured to store a plurality of first bytes and a secondbuffer configured to store a plurality of second bytes.
 15. The methodaccording to claim 12, further comprising the step of: reassembling saidpixel data from said first byte and said second byte.
 16. The methodaccording to claim 12, further comprising the steps of: generating acompressed bitstream from a plurality of first bytes; and storing saidcompressed bitstream in said memory.
 17. The method according to claim12, further comprising the steps of: reading a compressed bitstream fromsaid memory; and generating an 8-bit data stream in response to acompressed bitstream.
 18. The method according to claim 17, furthercomprising the steps of: generating a multi-bit data stream from said8-bit data stream using dithering; and generating a video output signalin response to said multi-bit data stream.
 19. The method according toclaim 18, wherein said video output signal is generated in response to(i) said pixel data in a first mode, (ii) reconstructed pixel data in asecond mode and (iii) said multi-bit data stream in a third mode. 20.The method according to claim 18, wherein said dither comprises at leastone of (i) adding random noise to the least significant bits of saidmulti-bit data stream and (ii) adding zeroes as the least significantbits of said multi-bit data stream and performing horizontal andvertical filtering.